RISC-V (pronounced ‘risk-five’) is a popular open source computer processor architecture in the academic community. A dual-core RISC-V processor was used as the basis of the photonic processor we wrote about in HEXUS news just before Xmas. Now RISC-V “is on the march as an open source alternative to ARM and Mips,” reports the EE Times.
Tech giants Google, Hewlett Packard Enterprise (HPE), Lattice, Microsemi and Oracle are among the first 15 members of a new RISC-V trade group. Next week the group is hosting a workshop for the processor core. One of the current tasks of the group is to draft the open source agreement which will form part of its membership. The RISC-V is developed under an open source license and members will be able to verify and use the RISC-V logo.
If any of the trade group companies make changes to the RISC-V core designs they will have to share the information to the open source group. However there is still room for companies to add “secret sauce and company-specific implementations,” as they may wish, noted executive director of the RISC-V Foundation, Rick O’Connor.
RISC-V processors can currently be used to run Linux and NetBSD. Support for other OSes is planned for the coming year. There are six open CPU designs currently available which include the 64-bit ‘Rocket’ and five ‘Sodor’ CPUs. However, at the time of writing there is only one commercial shipping product using a RISC-V baded SoC, a digital camera. During the upcoming workshop, FPGA-based accelerators using embedded RISC-V cores will be under discussion.